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low capacitance, 4-/8-channel, 15 v/+12 v i cmos multiplexers adg1208/adg1209 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006C2009 analog devices, inc. all rights reserved. features <1 pc charge injection over full signal range 1 pf off capacitance 33 v supply range 120 on resistance fully specified at 15 v/+12 v 3 v logic compatible inputs rail-to-rail operation break-before-make switching action available in 16-lead tssop, 4 mm 4 mm lfcsp_vq, and 16-lead soic typical power consumption < 0.03 w applications audio and video routing automatic test equipment data-acquisition systems battery-powered systems sample-and-hold systems communication systems functional block diagrams adg1208 s1 s8 d adg1209 s1a s4b da db s4a s1b 1-of-4 decoder 1-of-8 decoder a0 a1 en a0 a1 a2 en 05713-001 figure 1. general description the adg1208 and adg1209 are monolithic, i cmos? analog multiplexers comprising eight single channels and four differential channels, respectively. the adg1208 switches one of eight inputs to a common output as determined by the 3-bit binary address lines a0, a1, and a2. the adg1209 switches one of four differential inputs to a common differential output as determined by the 2-bit binary address lines a0 and a1. an en input on both devices is used to enable or disable the device. when disabled, all channels are switched off. when on, each channel conducts equally well in both directions and has an input signal range that extends to the supplies. the i cmos (industrial cmos) modular manufacturing process combines high voltage cmos (complementary metal- oxide semiconductor) and bipolar technologies. it enables the development of a wide range of high performance analog ics capable of 33 v operation in a footprint that no other generation of high voltage parts has been able to achieve. unlike analog ics using conventional cmos processes, i cmos components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. the ultralow capacitance and exceptionally low charge injection of these multiplexers make them ideal solutions for data acquisition and sample-and-hold applications, where low glitch and fast settling are required. figure 2 shows that there is minimum charge injection over the entire signal range of the device. i cmos construction also ensures ultralow power dissipation, making the parts ideally suited for portable and battery- powered instruments. v s (v) charge injection (pc) 1.0 0 ?15 15 05713-051 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 ?10 ?5 0 5 10 mux (source to drain) t a = 25c v dd =+15v v ss = ?15v v dd =+5v v ss =?5v v dd =+12v v ss =0v figure 2. source to drain charge injection vs. source voltage
adg1208/adg1209 rev. b | page 2 of 20 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagrams ............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? dual supply ................................................................................... 3 ? single supply ................................................................................. 5 ? absolute maximum ratings ............................................................7 ? esd caution...................................................................................7 ? pin configurations and function descriptions ............................8 ? typical performance characteristics ........................................... 10 ? terminology .................................................................................... 14 ? test circuits ..................................................................................... 15 ? outline dimensions ....................................................................... 17 ? ordering guide .......................................................................... 18 ? revision history 1/09rev. a to rev. b change to i dd parameter, table 1 ................................................... 4 change to i dd parameter, table 2 ................................................... 6 4/07rev. 0 to rev. a added 16-lead soic .......................................................... universal changes to table 1 ............................................................................ 3 changes to table 2 ............................................................................ 5 changes to figure 10 and figure 11 ............................................. 10 updated outline dimensions ....................................................... 17 changes to ordering guide .......................................................... 18 4/06revision 0: initial version
adg1208/adg1209 rev. b | page 3 of 20 specifications dual supply v dd = +15 v 10%, v ss = C15 v 10%, gnd = 0 v, unless otherwise noted. 1 table 1. parameter +25oc ?40oc to +85oc ?40oc to +125oc unit test conditions/comments analog switch analog signal range v ss to v dd v on resistance, r on 120 typ v s = 10 v, i s = ?1 ma, see figure 29 200 240 270 max v dd = +13.5 v, v ss = ?13.5 v on resistance match between channels, ?r on 3.5 typ v s = 10 v, i s = ?1 ma 6 10 12 max on resistance flatness, r flat (on) 20 typ v s = ?5 v/0 v/+5 v, i s = ?1 ma 64 76 83 max leakage currents source off leakage, i s (off ) 0.003 na typ v d = 10 v, v s = ?10 v, see figure 30 0.1 0.6 1 na max drain off leakage, i d (off ) 0.003 na typ v s = 1 v/10 v, v d = 10 v/1 v, see figure 30 adg1208 0.1 0.6 1 na max adg1209 0.1 0.6 1 na max channel on leakage, i d , i s (on) 0.02 na typ v s = v d = 10 v, see figure 31 adg1208 0.2 0.6 1 na max adg1209 0.2 0.6 1 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.005 a max v in = v inl or v inh 0.1 a max digital input capacitance, c in 2 pf typ dynamic characteristics 2 transition time, t transition 80 ns typ r l = 300 , c l = 35 pf 130 165 185 ns max v s = 10 v, see figure 32 t on (en) 75 ns typ r l = 300 , c l = 35 pf 95 105 115 ns max v s = 10 v, see figure 34 t off (en) 83 ns typ r l = 300 , c l = 35 pf 100 125 140 ns max v s = 10 v, see figure 34 break-before-make time delay, t bbm 25 ns typ r l = 300 , c l = 35 pf 10 ns min v s1 = v s2 = 10 v, see figure 33 charge injection 0.4 pc typ v s = 0 v, r s = 0 , c l = 1 nf, see figure 35 off isolation ?85 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 36 channel-to-channel crosstalk ?85 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 38 total harmonic distortion + noise 0.15 % typ r l = 10 k, 5 v rms, f = 20 hz to 20 khz, see figure 39 ?3 db bandwidth 550 mhz typ r l = 50 , c l = 5 pf, see figure 37 c s (off ) 1 pf typ f = 1 mhz, v s = 0 v 1.5 pf max f = 1 mhz, v s = 0 v c d (off ) adg1208 6 pf typ f = 1 mhz, v s = 0 v 7 pf max f = 1 mhz, v s = 0 v c d (off ) adg1209 3.5 pf typ f = 1 mhz, v s = 0 v 4.5 pf max f = 1 mhz, v s = 0 v
adg1208/adg1209 rev. b | page 4 of 20 parameter +25oc ?40oc to +85oc ?40oc to +125oc unit test conditions/comments c d , c s (on) adg1208 7 pf typ f = 1 mhz, v s = 0 v 8 pf max f = 1 mhz, v s = 0 v c d , c s (on) adg1209 5 pf typ f = 1 mhz, v s = 0 v 6 pf max f = 1 mhz, v s = 0 v power requirements v dd = +16.5 v, v ss = ?16.5 v i dd 0.002 a typ digital inputs = 0 v or v dd 1.0 a max i dd 220 a typ digital inputs = 5 v 380 a max i ss 0.002 a typ digital inputs = 0 v or v dd 1.0 a max i ss 0.002 a typ digital inputs = 5 v 1.0 a max v dd /v ss 5/16.5 v min/max |v dd | = |v ss | 1 temperature range is as follows: y version: C40c to +125c. 2 guaranteed by design, not subject to production test.
adg1208/adg1209 rev. b | page 5 of 20 single supply v dd = 12 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. 1 table 2. parameter +25oc ?40oc to +85oc ?40oc to +125oc unit test conditions/comments analog switch analog signal range 0 to v dd v on resistance, r on 300 typ v s = 0 v to 10 v, i s = ?1 ma, see figure 29 475 567 625 max v dd = 10.8 v, v ss = 0 v on resistance match between channels, ?r on 5 typ v s = 0 v to 10 v, i s = ?1 ma 16 26 27 max on resistance flatness, r flat (on) 60 typ v s = 3 v/6 v/9 v, i s = ?1 ma leakage currents v dd = 13.2 v source off leakage, i s (off ) 0.003 na typ v s = 1 v/10 v, v d = 10 v/1 v, see figure 30 0.1 0.6 1 na max drain off leakage, i d (off ) 0.003 na typ v s = 1 v/10 v, v d = 10 v/1 v, see figure 30 adg1208 0.1 0.6 1 na max adg1209 0.1 0.6 1 na max channel on leakage i d , i s (on) 0.02 na typ v s = v d = 1 v or 10 v, see figure 31 adg1208 0.2 0.6 1 na max adg1209 0.2 0.6 1 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.001 0.1 a max v in = v inl or v inh digital input capacitance, c in 3 pf typ dynamic characteristics 2 transition time, t transition 100 ns typ r l = 300 , c l = 35 pf 170 210 235 v s = 8 v, see figure 32 t on (en) 90 ns typ r l = 300 , c l = 35 pf 110 140 160 v s = 8 v, see figure 34 t off (en) 105 ns typ r l = 300 , c l = 35 pf 130 155 175 v s = 8 v, see figure 34 break-before-make time delay, t bbm 45 ns typ r l = 300 , c l = 35 pf 20 ns min v s1 = v s2 = 8 v, see figure 33 charge injection ?0.2 pc typ v s = 6 v, r s = 0 , c l = 1 nf, see figure 35 off isolation ?85 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 36 channel-to-channel crosstalk ?85 db typ r l = 50 , c l = 5 pf, f = 1 mhz, see figure 38 ?3 db bandwidth 450 mhz typ r l = 50 , c l = 5 pf, see figure 37 c s (off ) 1.2 pf typ f = 1 mhz, v s = 6 v 1.8 pf max f = 1 mhz, v s = 6 v c d (off ) adg1208 7.5 pf typ f = 1 mhz, v s = 6 v 9 pf max f = 1 mhz, v s = 6 v c d (off ) adg1209 4.5 pf typ f = 1 mhz, v s = 6 v 5.5 pf max f = 1 mhz, v s = 6 v c d , c s (on) adg1208 9 pf typ f = 1 mhz, v s = 6 v 10.5 pf max f = 1 mhz, v s = 6 v c d , c s (on) adg1209 6 pf typ f = 1 mhz, v s = 6 v 7.5 pf max f = 1 mhz, v s = 6 v
adg1208/adg1209 rev. b | page 6 of 20 parameter +25oc ?40oc to +85oc ?40oc to +125oc unit test conditions/comments power requirements v dd = 13.2 v i dd 0.002 a typ digital inputs = 0 v or v dd 1.0 a max i dd 220 a typ digital inputs = 5 v 380 a max v dd 5/16.5 v min/max v ss = 0 v, gnd = 0 v 1 temperature range is as follows: y version: C40c to +125c. 2 guaranteed by design, not subject to production test.
adg1208/adg1209 rev. b | page 7 of 20 absolute maximum ratings t a = 25c, unless otherwise noted. table 3. parameter rating v dd to v ss 35 v v dd to gnd ?0.3 v to +25 v v ss to gnd +0.3 v to ?25 v analog, digital inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma (whichever occurs first) continuous current, s or d 30 ma peak current, s or d (pulsed at 1 ms, 10% duty cycle maximum) 100 ma operating temperature range industrial (y version) C40c to +125c storage temperature C65c to +150c junction temperature 150c ja , thermal impedance, tssop 112c/w ja , thermal impedance, lfcsp_vq 30.4c/w ja , thermal impedance, soic_n 77c/w reflow soldering peak temperature (pb-free) 260(+0/?5)c 1 overvoltages at a, en, s, or d are cl amped by internal diodes. current should be limited to the maximum ratings given. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
adg1208/adg1209 rev. b | page 8 of 20 pin configurations and function descriptions 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 en 9 v ss s1 s4 s3 s2 a0 a2 gnd v dd s7 s6 s5 a1 adg1208 top view (not to scale) ds 8 0 5713-002 pin 1 indicator 1 figure 3. adg1208 pin configuration (tssop/soic) v ss 2 s1 3 s2 4 s3 11 v dd 12 gnd 10 s5 9s6 5 s 4 6 d 7 s 8 8 s 7 1 5 a 0 1 6 e n 1 4 a 1 1 3 a 2 top view (not to scale) adg1208 05713-004 figure 4. adg1208 pin configuration (lfcsp_vq), exposed pad tied to substrate, v ss table 4. adg1208 pin function descriptions pin number tssop/soic lfcsp_vq mnemonic description 1 15 a0 logic control input. 2 16 en active high digital input. when low, the device is disabled and all switches are off. when high, ax logic inputs determine on switches. 3 1 v ss most negative power supply potential. in single-supply applications, it can be connected to ground. 4 2 s1 source terminal 1. can be an input or an output. 5 3 s2 source terminal 2. can be an input or an output. 6 4 s3 source terminal 3. can be an input or an output. 7 5 s4 source terminal 4. can be an input or an output. 8 6 d drain terminal. can be an input or an output. 9 7 s8 source terminal 8. can be an input or an output. 10 8 s7 source terminal 7. can be an input or an output. 11 9 s6 source terminal 6. can be an input or an output. 12 10 s5 source terminal 5. can be an input or an output. 13 11 v dd most positive power supply potential. 14 12 gnd ground (0 v) reference. 15 13 a2 logic control input. 16 14 a1 logic control input. table 5. adg1208 truth table a2 a1 a0 en on switch x x x 0 none 0 0 0 1 1 0 0 1 1 2 0 1 0 1 3 0 1 1 1 4 1 0 0 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 8
adg1208/adg1209 rev. b | page 9 of 20 1 2 3 4 5 6 7 8 16 15 14 13 12 en v ss s1a s2a a0 gnd v dd s1b s2b a1 adg1209 top view (not to scale) 11 10 9 s4a s3a s4b da db s3b 0 5713-003 pin 1 indicator 1v ss 2 s1a 3 s2a 4 s3a 11 s1b 12 v dd 10 s2b 9s3b 1 5 a 0 1 6 e n 1 4 a 1 1 3 g n d top view (not to scale) adg1209 figure 5. adg1209 pin configuration (tssop/soic) 5 s 4 a 6 d a 7 d b 8 s 4 b 05713-005 figure 6. adg1209 pin configurations (lfcsp_vq), exposed pad tied to substrate, v ss table 6. adg1209 pin function descriptions pin number tssop/soic lfcsp_vq mnemonic description 1 15 a0 logic control input. 2 16 en active high digital input. when low, the device is disabled and all switches are off. when high, ax logic inputs determine on switches. 3 1 v ss most negative power supply potential. in single-supply applications, it can be connected to ground. 4 2 s1a source terminal 1a. ca n be an input or an output. 5 3 s2a source terminal 2a. ca n be an input or an output. 6 4 s3a source terminal 3a. ca n be an input or an output. 7 5 s4a source terminal 4a. ca n be an input or an output. 8 6 da drain terminal a. can be an input or an output. 9 7 db drain terminal b. can be an input or an output. 10 8 s4b source terminal 4b. ca n be an input or an output. 11 9 s3b source terminal 3b. ca n be an input or an output. 12 10 s2b source terminal 2b. can be an input or an output. 13 11 s1b source terminal 1b. can be an input or an output. 14 12 v dd most positive power supply potential. 15 13 gnd ground (0 v) reference. 16 14 a1 logic control input. table 7. adg1209 truth table a1 a0 en on switch pair x x 0 none 0 0 1 1 0 1 1 2 1 0 1 3 1 1 1 4
adg1208/adg1209 rev. b | page 10 of 20 8 typical performance characteristics source or drain voltage (v) on resistance ( ? ) 200 100 0 ?18 ?15 ?12 ?9 ?6 ?3 12 15 9 06 31 180 160 140 120 80 60 40 20 t a = 25c v dd = +15v v ss =?15v v dd = +16.5v v ss = ?16.5v v dd = +13.5v v ss = ?13.5v 05713-030 figure 7. on resistance as a function of v d (v s ) for dual supply source or drain voltage (v) on resistance ( ? ) 600 300 0 ?6 ?4 ?2 4 02 6 500 400 200 100 t a = 25c v dd =+5v v ss =?5v v dd =+5.5v v ss = ?5.5v v dd = +4.5v v ss =?4.5v 05713-031 figure 8. on resistance as a function of v d (v s ) for dual supply source or drain voltage (v) on resistance ( ? ) 450 250 300 0 02 46 12 810 14 400 350 150 200 100 50 t a = 25c v dd =12v v ss =0v v dd =13.2v v ss =0v v dd =10.8v v ss =0v 05713-032 figure 9. on resistance as a function of v d (v s ) for single supply source or drain voltage (v) on resistance ( ? ) 250 0 ?15 ?10 ?5 10 05 15 150 200 100 50 t a = +25c t a = +85c t a = +125c t a = ?40c v dd = +15v v ss = ?15v 05713-033 figure 10. on resistance as a function of v d (v s ) for different temperatures, dual supply source or drain voltage (v) on resistance ( ? ) 600 0 024 10 68 12 300 400 200 500 100 t a = +25c t a = +85c t a = +125c t a = ?40c v dd = 12v v ss = 0v 05713-034 figure 11. on resistance as a function of v d (v s ) for different temperatures, single supply 400 ?400 0 102030405060708090100110120 temperature (c) leakage current (pa) 300 200 100 0 ?100 ?200 ?300 i s (off) + ? i d (off) + ? i d , s (on) + + i s (off) ? + i d , s (on) ? ? i d (off) ? + 05713-057 v dd = +15v v ss = ?15v v bias = +10v/?10v figure 12. adg1208 leakage currents as a fu nction of temperature, dual supply
adg1208/adg1209 rev. b | page 11 of 20 150 ?150 0 102030405060708090100110120 temperature (c) leakage current (pa) 100 50 0 ?50 ?100 i s (off) + ? i d (off) + ? i s (off) ? + i d (off) ? + i d , s (on) ? ? i d , s (on) + + 05713-058 v dd = 12v v ss = 0v v bias = 1v/10v figure 13. adg1208 leakage currents as a function of temperature, single supply 0 5713-035 logic, in x (v) i dd (a) 200 60 80 100 120 140 160 180 40 20 0 0 2 4 6 8 10121416 v dd = +12v v ss =0v v dd =+15v v ss = ?15v i dd per channel t a =25 c figure 14. i dd vs. logic level v s (v) charge injection (pc) 1.0 0 ?15 15 05713-040 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 ?10 ?5 0 5 10 mux (source to drain) t a = 25c v dd = +15v v ss = ?15v v dd =+5v v ss =?5v v dd = +12v v ss =0v figure 15. source-to-drain charge injection vs. source voltage v s (v) charge injection (pc) 6 ?6 ?15 15 05713-041 ?10 ?5 0 5 10 demux (drain to source) t a = 25c 4 2 0 ?2 ?4 v dd = +15v v ss =?15v v dd =+5v v ss = ?5v v dd =+12v v ss =0v figure 16. drain-to-source charge injection vs. source voltage 350 0 ?40 temperature (c) time (ns) 300 250 200 150 100 50 ?20 0 20 40 60 80 100 120 v dd =+5v v ss =?5v v dd =+12v v ss =0v v dd =+15v v ss = ?15v 05713-052 figure 17. t on /t off times vs. temperature 0 5713-049 frequency (hz) off isolation (db) 0 ?10 ?20 ?30 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 10k 100k 1m 10m 100m 1g v dd = +15v v ss = ?15v t a =25 c figure 18. off isol ation vs. frequency
adg1208/adg1209 rev. b | page 12 of 20 frequency (hz) crosstalk (db) 20 ?120 10k 1g 05713-042 100k 1m 10m 100m 0 ?20 ?40 ?60 ?80 ?100 v dd =+15v v ss = ?15v t a =25c adjacent channels nonadjacent channels figure 19. adg1208 crosstalk vs. frequency 0 ?120 10k 1g frequency (hz) crosstalk (db) ?20 ?40 ?60 ?80 ?100 100k 1m 10m 100m adjacent channels nonadjacent channels 05713-053 figure 20. adg1209 crosstalk vs. frequency ? 6.0 ?10.0 10k 1g frequency (hz) on response (db) ?6.5 ?7.0 ?7.5 ?8.0 ?8.5 ?9.0 ?9.5 100k 1m 10m 100m 05713-054 figure 21. on response vs. frequency frequency (hz) thd + n (%) 10 1 0.1 0.01 10 100 1k 10k 100k load = 10k ? t a = 25c v dd =+5v,v ss = ?5v, v s = +3.5vrms v dd = +15v, v ss = ?15v, v s =+5vrms 05713-036 figure 22. thd + n vs. frequency v bias (v) capacitance (pf) 12 0 ?15 15 05713-043 ?10 ?5 0 5 10 10 8 6 4 2 source/drain on drain off source off v dd = +15v v ss = ?15v t a =25c figure 23. adg1208 capacitance vs. source voltage, 15 v dual supply v bias (v) capacitance (pf) 12 0 01 05713-045 2 246810 10 8 6 4 2 v dd =12v v ss =0v t a = 25c source/drain on drain off source off figure 24. adg1208 capacitance vs. source voltage, 12 v single supply
adg1208/adg1209 rev. b | page 13 of 20 12 0 ?5 5 v bias (v) capacitance (pf) 10 8 6 4 2 ?4 ?3 ?2 ?1 0 1 2 3 4 v dd =+5v v ss = ?5v t a = 25c source off drain off source/drain on 05713-055 figure 25. adg1208 capacitance vs. source voltage, 5 v dual supply v bias (v) capacitance (pf) 8 0 ?15 15 05713-046 ?10 ?5 0 5 10 v dd = +15v v ss = ?15v t a =25c 7 6 5 4 3 2 1 source/drain on drain off source off figure 26. adg1209 capacitance vs. source voltage, 15 v dual supply v bias (v) capacitance (pf) 8 0 01 05713-047 2 246810 v dd =12v v ss =0v t a =25c 7 6 5 4 3 2 1 source off drain off source/drain on figure 27. adg1209 capacitance vs. so urce voltage, 12 v single supply 8 0 ?5 5 v bias (v) capacitance (pf) ?4 ?3 ?2 ?1 0 1 2 3 4 v dd =+5v v ss = ?5v t a = 25c source off drain off source/drain on 7 6 5 4 3 2 1 05713-056 figure 28. adg1209 capacitance vs. source voltage, 5 v dual supply
adg1208/adg1209 rev. b | page 14 of 20 terminology r on ohmic resistance between d and s. r on difference between the r on of any two channels. i s (off) source leakage current when the switch is off. i d (off) drain leakage current when the switch is off. i d , i s (on) channel leakage current when the switch is on. v d (v s ) analog voltage on terminal d, terminal s. c s (off) channel input capacitance for off condition. c d (off) channel output capacitance for off condition. c d , c s (on) on switch capacitance. c in digital input capacitance. t on (en) delay time between the 50% and 90% points of the digital input and switch on condition. t off (en) delay time between the 50% and 90% points of the digital input and switch off condition. t transition delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. t bbm off time measured between the 80% point of both switches when switching from one address state to another. v inl maximum input voltage for logic 0. v inh minimum input voltage for logic 1. i inl (i inh ) input current of the digital input. i dd positive supply current. i ss negative supply current. off isolation a measure of unwanted signal coupling through an off channel. charge injection a measure of the glitch impulse transferred from the digital input to the analog output during switching. bandwidth the frequency at which the output is attenuated by 3 db. on response the frequency response of the on switch. total harmonic distortion + noise (thd + n) the ratio of the harmonic amplitude plus noise of the signal to the fundamental.
adg1208/adg1209 rev. b | page 15 of 20 test circuits i ds sd v s v 05713-037 figure 29. on resistance sd v s a a v d i s (off) i d (off) 05713-038 figure 30. off leakage sd a v d i d (on) nc nc = no connect 05713-039 figure 31. on leakage 3v 0v output t r < 20ns t f <20ns address drive (v in ) t transition t transition 50% 50% 90% 90% output adg1208 1 a0 a1 a2 50 ? 300 ? gnd s1 s2?s7 s8 d 35pf v in 2.4v en v dd v ss v dd v ss v s1 v s8 1 similar connection for adg1209. 05713-022 figure 32. address to ou tput switching times, t transition output adg1208 1 a0 a1 a2 50? 300 ? gnd s1 s2?s7 s8 d 35pf v in 2.4v en v dd v ss v dd v ss v s 1 similar connection for adg1209. 3v 0v output 80% 80% address drive (v in ) t bbm 05713-023 figure 33. break-before-make delay, t bbm output adg1208 1 a0 a1 a2 50? 300? gnd s1 s2?s8 d 35pf v in en v dd v ss v dd v ss v s 1 similar connection for adg1209. 3v 0v o utput 50% 50% t off (en) t on (en) 0.9v o 0.9v o enable d r ive (v in ) 05713-024 figure 34. enable delay, t on (en), t off (en)
adg1208/adg1209 rev. b | page 16 of 20 3v v in v out q inj =c l v out v out d s en gnd c l 1nf v out v in r s v s v dd v ss v dd v ss a0 a1 a2 adg1208 1 1 similar connection for adg1209. 05713-025 figure 35. charge injection v out 50? network analyzer r l 50? s d 50 ? off isolation = 20 log v out v s v s v dd v ss 0.1f v dd 0.1f v ss gnd 05713-026 figure 36. off isolation v out 50? network analyzer r l 50 ? s d insertion loss = 20 log v out with switch v out without switch v s v dd v ss 0.1f v dd 0.1f v ss gnd 05713-027 figure 37. bandwidth channel-to-channel crosstalk = 20 log v out gnd s1 d s2 v out network analyzer r l 50 ? r 50? v s v s v dd v ss 0.1f v dd 0.1f v ss 05713-028 figure 38. channel-to-channel crosstalk v out r s audio precision r l 10k? in v in s d v s vp-p v dd v ss 0.1f v dd 0.1f v ss gnd 05713-029 figure 39. thd + noise
adg1208/adg1209 rev. b | page 17 of 20 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 40. 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters compliant to jedec standards mo-220-vggc 2 . 2 5 2 . 1 0 s q 1 . 9 5 16 5 13 8 9 12 1 4 1.95 bsc pin 1 indicator top view 4.00 bsc sq 3.75 bsc sq coplanarity 0.08 (bottom view) 12 max 1.00 0.85 0.80 seating plane 0.35 0.30 0.25 0.80 max 0.65 typ 0.05 max 0.02 nom 0.20 ref 0.65 bsc 0.60 max 0.60 max pin 1 indicator 0.25 min 021207-a 0.75 0.60 0.50 figure 41. 16-lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad (cp-16-4) dimensions shown in millimeters controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-ac 10.00 (0.3937) 9.80 (0.3858) 16 9 8 1 6.20 (0.2441) 5.80 (0.2283) 4.00 (0.1575) 3.80 (0.1496) 1.27 (0.0500) bsc seating plane 0.25 (0.0098) 0.10 (0.0039) 0.51 (0.0201) 0.31 (0.0122) 1.75 (0.0689) 1.35 (0.0531) 0.50 (0.0197) 0.25 (0.0098) 1.27 (0.0500) 0.40 (0.0157) 0.25 (0.0098) 0.17 (0.0067) coplanarity 0.10 8 0 060606-a 45 figure 42. 16-lead standard small outline package [soic_n] narrow body (r-16) dimensions shown in millimeters and (inches)
adg1208/adg1209 rev. b | page 18 of 20 ordering guide model temperature range packag e description package option adg1208yruz 1 ?40c to +125c 16-lead thin shrink small outline package [tssop] ru-16 adg1208yruz-reel7 1 ?40c to +125c 16-lead thin shrink small outline package [tssop] ru-16 adg1208ycpz-reel 1 ?40c to +125c 16-lead lead frame chip scale package [lfcsp_vq] cp-16-4 adg1208ycpz-reel7 1 ?40c to +125c 16-lead lead frame chip scale package [lfcsp_vq] cp-16-4 adg1208yrz 1 ?40c to +125c 16-lead narrow body small outline package [soic_n] r-16 adg1208yrz-reel7 1 ?40c to +125c 16-lead narrow body small outline package [soic_n] r-16 adg1209yruz 1 ?40c to +125c 16-lead thin shrink small outline package [tssop] ru-16 adg1209yruz-reel7 1 ?40c to +125c 16-lead thin shrink small outline package [tssop] ru-16 adg1209ycpz-reel 1 ?40c to +125c 16-lead lead frame chip scale package [lfcsp_vq] cp-16-4 ADG1209YCPZ-REEL7 1 ?40c to +125c 16-lead lead frame chip scale package [lfcsp_vq] cp-16-4 adg1209yrz 1 ?40c to +125c 16-lead narrow body small outline package [soic_n] r-16 adg1209yrz-reel7 1 ?40c to +125c 16-lead narrow body small outline package [soic_n] r-16 1 z = rohs compliant part.
adg1208/adg1209 rev. b | page 19 of 20 notes
adg1208/adg1209 rev. b | page 20 of 20 notes ?2006C2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05713-0-1/09(b)

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